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PEDL9050-02
PEDL9050-02 This version: Dec. 1999 ML9050/9051 Previous version: Jun. 1999
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Semiconductor ML9050/9051
Semiconductor
132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
GENERAL DESCRIPTION
The ML9050/9051 is an LSI for dot matrix graphic LCD devices carrying out bit map display. This LSI can drive a dot matrix graphic LCD display panel under the control of an 8-bit microcomputer. Since all the functions necessary for driving a bit map type LCD device are incorporated in a single chip, using the ML9050/9051 makes it possible to realize a bit map type dot matrix graphic LCD display system with only a few chips. Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip, it is possible to construct a graphic display system with a maximum of 132 65 dots. The display can be expanded further using two chips. The ML9050/9051 is made using a CMOS process. Because it has a built-in RAM, low power consumption is one of its features, and is therefore suitable for displays in battery-operated portable equipment. The ML9050 has 65 common signal outputs and 132 segment signal outputs and one chip can drive a display of up to 65 132 dots. The ML9051 has 49 common signal outputs and 132 segment signal outputs and one chip can drive a display of up to 49 132 dots. This device is not resistant to radiation or to light.
FEATURES
* Direct display of the RAM data using the bit map method Display RAM data "1" ... Dot is displayed Display RAM data "0" ... Dot is not displayed * Display RAM capacity ML9050/9051: 65 132 = 8580 dots * LCD Drive circuits ML9050: 65 common outputs, 132 segment outputs ML9051: 49 common outputs, 132 segment outputs * Microcomputer interface: Can select an 8-Bit parallel or serial interface * Built-in voltage multiplier circuit for the LCD drive power supply * Built-in LCD drive power supply adjustment circuit * Built-in LCD drive bias resistors * Line reversal drive/frame reversal drive (selected by a command) * Built-in oscillator circuit (Internal RC oscillator/external clock input) * A variety of commands Read/write of display data, display ON/OFF, normal/reverse display, all dots ON/all dots OFF, set page address, set display start address, etc. * Power supply voltage Logic power supply: VDD-VSS = 1.8 V to 5.5 V Voltage multiplier reference voltage: VIN-VSS = 1.8 V to VDD (5-Times multiplier AE 1.8 V to 3.6 V, 6-times multiplier AE 1.8 to 3 V, 7-times multiplier AE 1.8 to 2.5 V) LCD Drive voltage: VBI-VSS = 6.0 to 18 V * Package: Gold bump chip, TCP 1/71
PEDL9050-02 Semiconductor ML9050/9051
BLOCK DIAGRAM
SEG131 COM63
VDD V1 V2 V3 V4 V5 VSS VC1+ VS1- VC2+ VS2- Display data latch circuit COM Output state selection cricuit SEG Drivers COM Drivers
Display timing generator circuit
COMS
COMS
COM0
SEG0
FRS FR CL DOF M/S
Power supply circuit
Page address circuit
VC3+ VC4+ VC5+ VC6+ VOUT VIN VR VRS IRS HPM
Display data RAM 132 65
Oscillator circuit
Column address circuit
Line address circuit
I/O Buffer
CLS
Bus holder
Command decoder
Status
MPU lnterface
WR(R/W)
D6(SCL)
D7(SI)
RD(E)
RES
CS1
CS2
C86
P/S
D5
D4
D3
D2
D1
D0
A0
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PEDL9050-02 Semiconductor ML9050/9051
PIN DESCRIPTION
Function
Pin name D0 to D7
Number of pins
I/O I/O
Description This is an 8-bit bi-directional data bus that can be connected to an 8-bit or 16-bit standard MPU data bus. When a serial interface is selected (P/S = "L"): D7: Serial data input pin (SI) D6: Serial clock input pin (SCL) In this case, D0 to D5 will be in the Hi-Z state. D0 to D7 will all be in the Hi-Z state when the chip select is in the inactive state.
MPU Interface
8
A0
1
I
Normally, the lowest bit of the MPU address bus is connected and used for distinguishing between data and commands. A0 = "H": Indicates that D0 to D7 is display data. A1 = "L": Indicates that D0 to D7 is control data.
RES CS1 CS2 RD (E)
1 2
I I
Initial setting is made by making RES = "L". The reset operation is made during the active level of the RES signal. These are the chip select signals. The Chip Select of the LSI becomes active when CS1 is "L" and also CS2 is "H" and allows the input/output of data or commands.
1
I
The active level of this signal is "L" when connected to an 80-series MPU. This terminal is connected to the RD signal of the 80-series MPU, and the data bus of the ML9050/9051 goes into the output state when this signal is "L". The active level of this signal is "H" when connected to a 68-series MPU. This pin will be the Enable and clock input pin when connected to a 68series MPU.
WR (R/W)
1
I
The active level of this signal is "L" when connected to an 80-series MPU. This terminal is connected to the WR signal of the 80-series MPU. The data on the data bus is latched into the ML9052 at the rising edge of the WR signal. When connected to a 68-series MPU, this pin becomes the input pin for the Read/Write control signal. R/W = "H": Read, R/W = "L": Write
C86
1
I
This is the pin for selecting the MPU interface type. C86 = "H": 68-Series MPU interface. C86 = "L": 80-Series MPU interface.
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PEDL9050-02 Semiconductor ML9050/9051
Function
Pin name P/S
Number of pins
I/O I
Description This is the pin for selecting parallel data input or serial data input. P/S = "H": Parallel data input. P/S = "L": Serial data input. The pins of the LSI have the following functions depending on the state of P/S input. P/S "H" "L" Data/command A0 A0 Data D0 to D7 SI (D7) Read/Write RD, WR Write only Serial clock SCL (D6)
MPU Interface
1
When P/S is "L", D0 to D5 will go into the Hi-Z state. In this condition, the data on the lines D0 to D5 can be "H", "L", or open. The pins RD (E) and WR (R/W) should be tied to either the "H" level or the "L" level. During serial data input, it is not possible to read the display data in the RAM. Oscillator circuit CLS 1 I This is the pin for selecting whether to enable or disable the internal oscillator circuit for the display clock. CLS = "H": The internal oscillator circuit is enabled. CLS = "L": The internal oscillator circuit is disabled (External input). When CLS = "L", the display clock is input at the pin CL. Display timing generator circuit M/S 1 I This is the pin for selecting whether master operation or slave operation is made towards the ML9050/9051. During master operation, the synchronization with the LCD display system is achieved by inputting the timing signals necessary for LCD display. M/S = "H": Master operation M/S = "L": Slave operation The functions of the different circuits and pins will be as follows depending on the states of M/S and CLS signals. M/S CLS "H" "L" "H" "L" "H" "L" Oscillator circuit Enabled Disabled Disabled Disabled Power supply circuit Enabled Enabled Disabled Disabled CL FR FRS DOF
Output Output Output Output Input Output Output Output Input Input Input Output Input Input Output Input
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PEDL9050-02 Semiconductor ML9050/9051
Function
Pin name CL
Number of pins
I/O I/O
Description This is the display clock input/output pin. The function of this pin will be as follows depending on the states of M/S and CLS signals. M/S CLS "H" "L" "L" "H" "L" CL Input Input Input
Display timing generator circuit
1
"H" Output
When the ML9050/9051 is used in the master/slave mode, the corresponding CL pin has to be connected. FR 1 I/O This is the input/output pin for LCD display frame reversal signal. M/S = "H": Output M/S = "L": Input When the ML9050/9051 is used in the master/slave mode, the corresponding FR pin has to be connected. DOF 1 I/O This is the blanking control pin for the LCD display. M/S = "H": Output M/S = "L": Input When the ML9050/9051 is used in the master/slave mode, the corresponding DOF pin has to be connected. FRS Power supply circuit IRS 1 1 O I This is the output pin for static drive. This pin is used in combination with the FR pin. This is the pin for selecting the resistor for adjusting the voltage V1. IRS = "H": The internal resistor is used. IRS = "L": The internal resistor is not used. The voltage V1 is adjusted using the external potential divider resistors connected to the pins VR. This pin is effective only in the master operation. This pin is tied to the "H" or the "L" level during slave operation. HPM 1 I This is the power control pin for the LCD drive power supply circuit. HPM = "H": Normal mode HPM = "L": High power mode This pin is effective only during master operation mode. This pin is tied to the "H" or the "L" level during slave operation. VDD VSS VIN 13 9 4 -- -- -- This pin is tied to the MPU power supply terminal VCC. This is the 0 V pin connected to the system ground (GND). This is the reference power supply of the voltage multiplier circuit for driving the LCD.
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PEDL9050-02 Semiconductor ML9050/9051
Function
Pin name VRS
Number of pins
I/O --
Description This is the external input VREG power supply for the LCD power supply voltage adjustment circuit. (This pin should be left open when not used as an external input) This pin is effective only in the case of optional devices with the VREG external input option.
Power supply circuit
2
VOUT V1 V2 V3 V4 V5
2 10
O --
These are the output pins during voltage multiplication. Connect a capacitor between these pins and VSS. These are the multiple level power supply pins for the LCD power supply. The voltages specified for the LCD cells are applied to these pins after resistor network voltage division or after impedance transformation using operational amplifiers. The voltages are specified taking VSS as the reference, and the following relationship should be maintained among them. V1 V2 V3 V4 V5 VSS Master operation: When the power supply is ON, the following voltages are applied to V2 to V5 from the built-in power supply circuit. The selection of voltages is determined by the LCD bias set command. ML9050 V2 V3 V4 V5 8/9 V1 7/9 V1 2/9 V1 1/9 V1 ML9051 V2 V3 V4 V5 7/8 V1 6/8 V1 2/8 V1 1/8 V1 5/6 V1 4/6 V1 2/6 V1 1/6 V1 6/7 V1 5/7 V1 2/7 V1 1/7 V1
VR
2
I
Voltage adjustment pins. Voltages between V1 and VSS are applied using a resistance voltage divider. These pins are effective only when the internal resistors for voltage V1 adjustment are not used (IRS = "L"). Do not use these pins when the internal resistors for voltage V1 adjustment are used (IRS = "H").
VC1+
2
O
These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS1- and these pins.
VS1-
2
O
These are the pins for connecting the negative side of the capacitors for voltage multiplication. Connect capacitors between these pins and VC1+, VC3+, and VC5+.
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PEDL9050-02 Semiconductor ML9050/9051
Function
Pin name VC2+
Number of pins
I/O O
Description These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS2- and these pins.
Power supply circuit
2
VS2-
2
O
These are the pins for connecting the negative side of the capacitors for voltage multiplication. Connect capacitors between these pins and VC2+, VC4+, and VC6+ (during 7-times voltage multiplication).
VC3+
2
O
These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS1- and these pins.
VC4+
2
O
These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS2- and these pins.
VC5+
2
O
These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS1- and these pins.
VC6+
2
O
These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS2- and these pins (during 7-times voltage multiplication). For 6-times voltage multiplication, connect these pins to the VOUT pin.
LCD Drive output
SEG0 to SEG131
132
O
These are the LCD segment drive outputs. One of the levels among V1, V3, V4, and VSS is selected depending on the combination of the display RAM content and the FR signal. RAM Data H H L L Power save FR H L H L -- Output voltage Normal display V1 VSS V3 V4 VSS Reverse display V3 V4 V1 VSS
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PEDL9050-02 Semiconductor ML9050/9051
Function
Pin name COM0 to COMn
Number of pins
I/O O
Description These are the LCD common drive outputs. COM ML9050 ML9051 COM0 to COM63 COM0 to COM47
LCD Drive output
96
One of the levels among V1, V2, V5, and VSS is selected depending on the combination of the scan data and the FR signal. Scan data H H L L Power save COMS 2 O FR H L H L -- Output voltage VSS V1 V2 V5 VSS
These are the COM output pins only for indicators. Both pins output the same signal. Leave these pins open when they are not used. The same signal is output in both master and slave operation modes.
Test pin
TEST0 TEST1
I O
These are the pins for testing the IC chip. Leave these pins open during normal use.
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PEDL9050-02 Semiconductor ML9050/9051
FUNCTIONAL DESCRIPTION
MPU Interface * Selection of interface type The ML9050/9051 carries out data transfer using either the 8-bit bi-directional data bus (D7 to D0) or the serial data input line (SI). Either the 8-bit parallel data input or serial data input can be selected as shown in Table 1 by setting the P/S pin to the "H" or the "L" level. Table 1
P/S H: Parallel input L: Serial input CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD RD -- WR WR -- C86 C86 -- D7 D7 SI D6 D6 SCL D5 to D0 D5 to D0 (HZ)
A hyphen (--) indicates that the pin can be tied to the "H" or the "L" level. * Parallel interface When the parallel interface is selected, (P/S = "H"), it is possible to connect this LSI directly to the MPU bus of either an 80-series MPU or a 68-series MPU as shown in Table 2 depending on whether the pin C86 is set to "H" or "L". Table 2
P/S H: 68-Series MPU bus L: 80-Series MPU bus CS1 CS1 CS1 CS2 CS2 CS2 A0 A0 A0 RD E RD WR R/W WR D7 to D0 D7 to D0 D7 to D0
The data bus signals are identified as shown in Table 3 below depending on the combination of the signals A0, RD(E), and WR(R/W) of Table 2. Table 3
Common 68-Series A0 Display data read Display data write Status read Control data write (command) 1 1 0 0 R/W 1 0 1 0 80-Series RD 0 1 0 1 WR 1 0 1 0
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PEDL9050-02 Semiconductor Serial interface When the serial interface is selected (P/S = "L"), the serial data input (SI) and the serial clock input (SCL) can be accepted if the chip is in the active state (CS1 = "L" and CS2 = "H"). The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data is read in from the serial data input pin in the sequence D7, D6, ... , D0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial clock pulse and processed further. The identification of whether the serial data is display data or command is judged based on the A0 input, and the data is treated as display data when A0 is "H" and as command when A0 is "L". The A0 input is read in and identified at the rising edge of the (8 n) th serial clock pulse after the chip has become active. Fig. 1 shows the signal chart of the serial interface. (When the chip is not active, the shift register and the counter are reset to their initial states. No data read out is possible in the case of the serial interface. It is necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL signal. We recommend verification of operation in an actual unit.)
CS1 CS2 SI SC A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
ML9050/9051
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Fig. 1 * Chip select The ML9050/9051 has the two chip select pins CS1 and CS2, and the MPU interface or the serial interface is enabled only when CS1 = "L" and CS2 = "H". When the chip select signals are in the inactive state, the D0 to D7 lines will be in the high impedance state and the inputs A0, RD, and WR will not be effective. When the serial interface has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state. * Accessing the display data RAM and the internal registers Accessing the ML9050/9051 from the MPU side requires merely that the cycle time (tCYC) be satisfied, and high speed data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the ML9050/9051 carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data bus. For example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus holder, and is then written into the display data RAM before the next data read cycle. Further, when the MPU reads out data in the display data RAM, first a dummy data read cycle is carried out to temporarily store the data in the bus holder which is then placed on the system bus and is read out during the next read cycle. There is a restriction on the read sequence of the display data RAM, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading. Therefore, always one dummy read is necessary immediately after setting the address or after a write cycle. This relationship is shown in Figs 2(a) and 2(b). 10/71
PEDL9050-02 Semiconductor * Data write
WR
MPU
ML9050/9051
DATA
Internal timing
N Latch N
N+1 N+1
N+2 N+2
N+3 N+3
BUS Holder Write Signal
Fig. 2(a) * Data read
WR
MPU
RD DATA Address Preset N N n n+1
Internal timing
Read Signal Column Address BUS Holder Preset N N Increment N+1 n n+1 N+2 n+2
Address Set #n
Dummy Read
Data Read #n
Data Read #n+1
Fig. 2(b) * Busy flag The busy flag being "1" indicates that the ML9050/9051 is carrying out internal operations, and hence no instruction other than a status read instruction is accepted during this period. The busy flag is output at pin D7 when a status read instruction is executed. If the cycle time (tCYC) is established, there is no need to check this flag before issuing every command and hence the processing performance of the MPU can be increased greatly.
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PEDL9050-02 Semiconductor Display data RAM * Display data RAM This is the RAM storing the dot data for display and has an organization of 65 (8 pages 8 bits +1) 132 bits. It is possible to access any required bit by specifying the page address and the column address. Since the display data D7 to D0 from the MPU corresponds to the LCD display in the direction of the common lines as shown in Fig. 3, there are fewer restrictions during display data transfer when the ML9050/9051 is used in a multiple chip configuration, thereby making it easily possible to realize a display with a high degree of freedom. Also, since the display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the signal read operation for the LCD drive. Consequently, the display is not affected by flickering, etc., even when the display data RAM is accessed asynchronously during the LCD display operation.
D0 D1 D2 D3 D4 0111---0 1000---0 0000---0 0111---0 1000---0 Display data RAM COM0 COM1 COM2 COM3 COM4 ----------LCD Display
ML9050/9051
Fig. 3 * Page address circuit The page address of the display data RAM is specified using the page address set command as shown in Fig. 4. Specify the page address again when accessing after changing the page. The page address 8 (D3, D2, D1, D0 AE 1, 0, 0, 0) is the RAM area dedicated to the indicator, and only the display data D0 is valid in this page. * Column address circuit The column address of the display data RAM is specified using the column address set command as shown in Fig. 4. Since the specified column address is incremented (by +1) every time a display data read/write command is issued, the MPU can access the display data continuously. Further, the incrementing of the column address is stopped at the column address of 83H. Since the column address and the page address are independent of each other, it is necessary, for example, to specify separately the new page address and the new column address when changing from column 83H of page 0 to column 00H of page 1. Also, as is shown in Table 4, it is possible to reverse the correspondence relationship between the display data RAM column address and the segment output using the ADC command (the segment driver direction select command). This reduces the IC placement restrictions at the time of assembling LCD modules. Table 4
SEG Output ADC D0 = "0" D0 = "1" SEG0 83(H) Column Address SEG131 0(H) 0(H) AE Column Address AE 83(H)
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PEDL9050-02 Semiconductor ML9050/9051
* Line address circuit The line address circuit is used for specifying the line address corresponding to the COM output when displaying the contents of the display data RAM as is shown in Fig. 4. Normally, the topmost line in the display (COM0 output in the normal display state of the common output, and COM63 output and COM47 output for the ML9050 and the ML9051, respectively, in the reverse display stage) is specified using the display start line address set command. The display area is 65 lines and 49 lines for the ML9050 and the ML9051, respectively, in the direction of increasing line address from the specified display start line address. It is possible to carry out screen scrolling and page changing by dynamically changing the line address using the display start line address set command. * Display data latch circuit The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being output to the LCD drive circuits. Since the commands for selecting normal/ reverse display and turning the display ON/OFF control the data in this latch, the data in the display data RAM will not be changed. Oscillator circuit This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when M/S = "H" and also CLS = "H". The oscillations will be stopped when CLS = "L", and the display clock has to be input to the CL pin.
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PEDL9050-02 Semiconductor ML9050/9051
Page Address Data D3 D2 D1 D0
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0
Line Address
When the common output state is normal display
COM Output
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS
0001
Page1
0010
Page2
0011
Page3
0100
Page4
0101
Page5
0110
Page6
0111
Page7
1000
Page8
10 D0 D0
ADC Column Address
83 00
82 01 81 02 80 03 7F 04 7E 05 7D 06 7C 07
7F 80 81 82 83
63Lines
48Lines
0000
Page0
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (Start) 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H
04 03 02 01 00
SEG127 SEG128 SEG129 SEG130 SEG131
Fig. 4 14/71
LCD Out
The 65th line and the 49th line for the ML9050 and the ML9051, respectively, accessed irrespective of the display start line address.
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
PEDL9050-02 Semiconductor Display timing generator circuit This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. The read out of the display data to the LCD drive circuits is completely independent of the display data RAM access from the MPU. As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed asynchronously during the LCD display. Also, the internal common timing and LCD frame reversal (FR) signals are generated by this circuit from the display clock. The drive waveforms of the frame reversal drive method shown in Fig. 5(a) for the LCD drive circuits are generated by this circuit. Further, the drive waveforms of the line reversal method shown in Fig. 5(b) can also be generated depending on the issued command. In the line reversal drive method, it is possible to carry out reverse display drive at every line to a maximum of 32 lines. Fig. 5(b) shows the waveforms of the 1 line reversal drive method. ML9050/9051
64 65 LCDCK (display clock) FR
1
2
3
4
5
6
60 61 62 63 64 65
1
2
3
4
5
6
V1 V2 COM0 V5 VSS V1 V2 COM1 V5 VSS RAM DATA V1 SEGn V3 V4 VSS
Fig. 5(a) Waveforms in the frame reversal drive method
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PEDL9050-02 Semiconductor ML9050/9051
64 65 LCDCK (display clock) FR
1
2
3
4
5
6
60 61 62 63 64 65
1
2
3
4
5
6
V1 V2 COM0 V5 VSS V1 V2 COM1 V5 VSS RAM DATA V1 SEGn V3 V4 VSS
Fig. 5(b) Waveforms in the line reversal drive method When the ML9050/9051 is used in a multiple chip configuration, it is necessary to supply the slave side display timing signals (FR, CL, and DOF) from the master side. The statuses of the signals FR, CL, and DOF are shown in Table 5. Table 5
Operating mode Master mode (M/S = "H") Internal oscillator circuit enabled (CLS = H) Internal oscillator circuit disabled (CLS = L) Slave mode (M/S = "L") Internal oscillator circuit enabled (CLS = H) Internal oscillator circuit disabled (CLS = L) FR Output Output Input Input CL Output Input Input Input DOF Output Output Input Input
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PEDL9050-02 Semiconductor Common output state selection circuit (see Table 6) Since the COM output scanning directions can be set using the common output state selection command in the ML9050/9051, it is possible to reduce the IC placement restrictions at the time of assembling LCD modules. Table 6
State Normal Display Reverse Display COM Scanning direction ML9050 COM0 AE COM63 COM63 AE COM0 ML9051 COM0 AE COM47 COM47 AE COM0
ML9050/9051
LCD Drive circuits This LSI incorporates 197 sets and 181 sets of multiplexers for the ML9050 and the ML9051, respectively, that generate 4-level outputs for driving the LCD. These output the LCD drive voltage in accordance with the combination of the display data, COM scanning signals, and the FR signal. Fig. 6 shows examples of the SEG and COM output waveforms in the frame reversal drive method.
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PEDL9050-02 Semiconductor ML9050/9051
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
FR
VDD VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 VSS V1 V2 V3 V4 V5 0V -V5 -V4 -V3 -V2 -V1 V1 V2 V3 V4 V5 0V -V5 -V4 -V3 -V2 -V1
COM0
COM1
COM2
SEG0
SEG1
SEG2
COM0-SEG0
COM0-SEG1
Fig. 6
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PEDL9050-02 Semiconductor Power supply circuit This is the low power consumption type power supply circuit for generating the voltages necessary for driving LCD devices, and consists of voltage multiplier circuits, voltage adjustment circuits, and voltage follower circuits. In the power supply circuit, it is possible to control the ON/OFF of each of the circuits of the voltage multiplier, voltage adjustment circuits, and voltage follower circuits using the power control set command. As a result, it is also possible to use parts of the functions of both the external power supply and the internal power supply. Table 7 shows the functions controlled by the 3-bit data of the power control set command and Table 8 shows a sample combination. Table 7 Details of functions controlled by the bits of the power control set command
Control bit D2 D1 D0 Function controlled by the bit Voltage multiplier circuit control bit Voltage adjustment circuit (V adjustment circuit) control bit Voltage follower circuit (V/F circuit) control bit
ML9050/9051
Table 8 Sample combination for reference
Circuit State used Only the internal power supply is used Only V adjustment and V/F circuits are used Only V/F circuits are used Only the external power supply is used D2 D1 D0 Voltage
V
External V/F voltage input VIN
Voltage multiplier pins *1 Used OPEN OPEN OPEN
multiplier Adjustment 1 0 0 0 1 1 0 0 1 1 1 0
VOUT V1 V1 to V5
*1:
The voltage multiplier pins are the pins VC1+, VS1-, VC2+, VS2-, VC3+, VC4+, VC5+, and VC6+. If combinations other than the above are used, normal operation is not guaranteed.
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* Voltage multiplier circuits The connections for 2-times to 7-times voltage multiplier circuits are shown below.
VIN VSS VOUT VC6+ VC4+ OPEN OPEN OPEN OPEN VC2+ VS2- VC5+ VC3+ VC1+ VS1- 2-times voltage multiplier circuit OPEN OPEN
VIN VSS VOUT VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- 3-times voltage multiplier circuit OPEN
VIN VSS VOUT VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- 4-times voltage multiplier circuit
VIN VSS VOUT VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- 5-times voltage multiplier circuit
VIN VSS VOUT VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- 6-times voltage multiplier circuit
VIN VSS VOUT VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- 7-times voltage multiplier circuit
Fig. 7
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The voltage relationships in voltage multiplication are shown in Fig. 8.
VOUT = 7 VIN = 17.5V VOUT = 6 VIN = 18 V
*1 VIN = 2.5 V VSS = 0 V Voltage relationship in 7-times multiplication
*1 VIN = 3 V VSS = 0 V Voltage relationship in 6-times multiplication
Fig. 8 *1: The voltage range of VIN should be set so that the voltage at the pin VOUT does not exceed the absolute maximum rating.
* Voltage adjustment circuit The voltage multiplier output VOUT produces the LCD drive voltage V1 via the voltage adjustment circuit. Since the ML9050/9051 incorporates a high accuracy constant voltage generator, a 64-level electronic potentiometer function, and also resistors for voltage V1 adjustment, it is possible to build a high accuracy voltage adjustment circuit with very few components. In addition, the ML9050/9051 is available in three models with the temperature gradients of - (1) about -0.05%/C, (2) about -0.2%/C, and (3) external input (input to pin VRS), as a VREG option. (a) When the internal resistors for voltage V1 adjustment are used It is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands and without needing any external resistors, if the internal voltage V1 adjustment resistors and the electronic potentiometer function are used. The voltage V1 can be obtained by the following equation A-1 in the range of V1Internal Rb
Internal Ra VSS
- +
V1
VEV (Constant voltage generator + electronic potentiometer)
Fig. 9 VREG is a constant voltage generated inside the IC and its value is constant as given in Table 9 at Ta = 25C.
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PEDL9050-02 Semiconductor Table 9
Temperature gradient -0.05 -0.2 --
ML9050/9051
Model (1) Internal power supply (2) Internal power supply (3) External input
Unit [%/C] [%/C] --
VREG 3.0 3.0 VRS
Unit [V] [V] [V]
Here, a is the electronic potentiometer function which allows one level among 64 levels to be selected by merely setting the data in the 6-bit electronic potentiometer register. The values of a set by the electronic potentiometer register are shown in Table 10.
Table 10
a 63 62 61 . . . 1 0 D5 0 0 0 . . . 1 1 D4 0 0 0 . . . 1 1 D3 0 0 0 . . . 1 1 D2 0 0 0 . . . 1 1 D1 0 0 1 . . . 1 1 D0 0 1 0 0 1
Rb/Ra is the voltage V1 adjustment internal resistor ratio and can be adjusted to one of 8 levels by the voltage V1 adjustment internal resistor ratio set command. The reference values of the ratio (1+Rb/Ra) according to the 3-bit data set in the voltage V1 adjustment internal resistor ratio setting register are listed in Table 11. Table 11 Voltage V1 adjustment internal resistor ratio setting register values and the ratio (1+Rb/Ra) (For reference)
ML9050 Register value D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 Temperature gradient of the model [unit: %/C] -0.05 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 -0.2 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VREG 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 *1 3.0 3.5 4.0 4.5 5.0 5.4 5.9 6.5 ML9051 Temperature gradient of the model [unit: %/C] -0.05 -0.2 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VREG *1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
*1:
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(b) When external resistors are used (voltage V1 adjustment internal resistors are not used) - Case 1 It is also possible to set the LCD drive power supply voltage V1 without using the internal resistors for voltage V1 adjustment but connecting external resistors (Ra' and Rb') between VSS & VR and between VR & V1. Even in this case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic potentiometer function is used. The voltage V1 can be obtained by the following equation B-1 in the range of V1External Rb' VR External Ra' VSS
- +
V1
VEV (Constant voltage generator + electronic potentiometer)
Fig. 10 Setting example: Setting V1 = 7 V at Ta = 25C using an ML9050/9051 of the model with a temperature gradient of -0.05%/C. When the electronic potentiometer register value is set to the middle value of (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), the value of a will be 31 and that of VREG will be 3.0 V, and hence the equation B-1 becomes as follows: V1 = (1+(Rb'/Ra')) * (1-(a/324)) * VREG 7 = (1+(Rb'/Ra')) * (1-(31/324)) * 3.0 (Eqn. B-2) Further, if the current flowing through Ra' and Rb' is set as 5mA, the value of Ra'+Rb' will be Ra'+Rb' = 1.4MW (Eqn. B-3) and hence, Rb'/Ra' = 1.58, Ra' = 543kW, Rb' = 857kW. In this case, the variability range of voltage V1 using the electronic potentiometer function and the increment size will be as given in Table 12. Table 12
V1 Variability range Increment size Min 6.24 (level 0) Typ 7.0 (center value) 24 Max 7.74 (level 63) Unit [V] [mV]
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(c) When external resistors are used (voltage V1 adjustment internal resistors are not used) - Case 2 It is possible to set the LCD drive power supply voltage V1 using fine adjustment of Ra' and Rb' by adding a variable resistor to the case of using external resistors in the above case. Even in this case, it is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands if the electronic potentiometer function is used. The voltage V1 can be obtained by the following equation C-1 in the range of V1External R3 Rb' External R2 VR Ra' External R1 VEV (Constant voltage generator + electronic potentiometer) D R2
- +
V1
VSS
Fig. 11 Setting example: Setting V1 in the range 5 V to 9 V using R2 at Ta = 25C using an ML9050/9051 of the model with a temperature gradient of -0.05%/C. When the electronic potentiometer register value is set to the middle value of (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), the value of a will be 31 and that of VREG will be 3.0 V, and hence in order to make V1 = 9 V when DR2 = 0W, the equation C-1 becomes as follows: 9 = (1+(R3+R2)/R1) * (1-(31/324)) * (3.0) (Eqn. C-2) In order to make V1 = 5 V when DR2 = R2, 5 = (1+R3/(R1+R2)) * (1-(31/324)) * (3.0) (Eqn. C-3) Further, if the current flowing between VSS and V1 is set as 5 mA, the value of R1+R2+R3 becomesR1+R2+R3 = 1.8MW (Eqn. C-4) and hence, R1 = 542kW, R2 = 436kW, R3 = 822kW. In this case, the variability range of voltage V1 using the electronic potentiometer function and the increment size will be as given in Table 13. Table 13
V1 Variability range Increment size Min 4.45 (level 0) 17 Typ 7.0 (center value) 24 Max 9.96 (level 63) 31 Unit [V] [mV]
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* When using the voltage V1 adjustment internal resistors or the electronic potentiometer function, it is necessary to set at least the voltage adjustment circuit and the voltage follower circuits both in the operating state using the power control setting command. Also, when the voltage multiplier circuit is OFF, it is necessary to supply a voltage externally to the VOUT pin. * The pin VR is effective only when the voltage V1 adjustment internal resistors are not used (pin IRS = "L"). Leave this pin open when the voltage V1 adjustment internal resistors are being used (pin IRS = "H"). * Since the input impedance of the pin VR is high, it is necessary to take noise countermeasures such as using short wiring length or a shielded wire . * LCD Drive voltage generator circuits The voltage V1 is divided using resistors inside the IC to generate the voltages V2, V3, V4, and V5 that are necessary for driving the LCD. In addition, these voltages V2, V3, V4, and V5 are impedance transformed using voltage follower circuits and fed to the LCD drive circuits. The bias ratio of 1/9 or 1/7 can be selected in the ML9050 and the bias ratio of 1/8 or 1/6 can be selected in the ML9051, using the LCD bias setting command. * High power mode The power supply circuit incorporated in the ML9050/9051 has an extremely low power consumption. [Normal mode: HPM = "H"]. Hence, in the case of an LCD device or panel with a large load, the display quality may become poorer. In such a case, setting the HPM pin to "L" (high power mode) can improve the quality of display. It is recommended to verify the display using an actual unit in order to decide whether or not to use this mode. Further, if the degree of display quality improvement is still not sufficient even after setting the high power mode, it is necessary to supply the LCD drive power supply from an external source. * Command sequence for shutting off the internal power supply When shutting off the internal power supply, it is recommended to use the procedure given in Fig. 11 of switching OFF the power after putting the LSI in the power save mode using the following command sequence.
Procedure Step1 O Step2 O End Description (Command, status) Display OFF O Display all ON O Internal power supply OFF 1 0 1 0 0 1 0 1 1 0 Command address D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1 0 Power save commands (multiple)
Fig. 12
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PEDL9050-02 Semiconductor * APPLICATION CIRCUITS
(1) When the voltage multiplier circuit, voltage adjustment circuit, and V/F circuits are all used When using the voltage V1 adjustement internal resistors VIN = VDD 7-Times voltage multiplication (2) When the voltage multiplier circuit, voltage adjustment circuit, and V/F circuits are all used When not using the voltage V1 adjustement internal resistors VIN = VDD 7-Times voltage multiplication
ML9050/9051
VDD IRS VIN VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- V1 VR VSS VOUT V1 V2 V3 V4 V5 M/S
VDD IRS VIN VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- V1 VR VSS VOUT V1 V2 V3 V4 V5 M/S
C1 C1 C1 C1 C1 C1
C1 C1 C1 C1 C1 C1 R1 VSS C1 C2 C2 C2 C2 C2 R2 R3
VSS C1 C2 C2 C2 C2 C2
C1: 1.0 to 4.7 m C2: 0.47 to 1.0 mF
C1: 1.0 to 4.7 m C2: 0.47 to 1.0 mF
(3) When only the voltage adjustment circuit and the V/F circuits are used When not using the voltage V1 adjustment internal resistors
(4) When only the V/F circuits are used When using the voltage V1 adjustment internal resistors
VDD VDD IRS VIN VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- V1 VR VSS VOUT V1 V2 V3 V4 V5 M/S IRS VIN VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- V1 VR VSS C2 C2 C2 C2 C2 VOUT V1 V2 V3 V4 V5 M/S
R1 R2 R3 VSS External power supply C2 C2 C2 C2 C2
External power supply VSS
C2: 0.47 to 1.0 mF
C2: 0.47 to 1.0 mF
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(5) When not using the internal power supply
VDD
IRS VIN VC6+ VC4+ VC2+ VS2- VC5+ VC3+ VC1+ VS1- V1 VR VSS VOUT V1 V2 V3 V4 V5
M/S
VSS
External power supply
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* Reset circuit This LSI goes into the initialized condition when the RES input goes to the "L" level. The initialized condition consists of the following conditions. (1) Display OFF (2) Normal display mode (3) ADC Select: Incremented (ADC command D0 = "L") (4) Power control register: (D2, D1, D0) = (0, 0, 0) (5) The registers and data in the serial interface are cleared. (6) LCD Power supply bias ratio: ML9050 ... 1/9 bias, ML9051 ... 1/8 bias (7) Read-modify-write: OFF (8) Static indicator: OFF Static indicator register: (D1, D2) = (0, 0) (9) Line 1 is set as the display start line. (10) The column address is set to address 0. (11) The page address is set to 0. (12) Common output state: Normal (13) Voltage V1 adjustment internal resistor ratio register: (D2, D1, D0) = (1, 0, 0) (14) The electronic potentiometer register set mode is released. Electronic potentiometer register: (D5, D4, D3, D2, D1, D0) = (1, 0, 0 ,0, 0, 0) (15) The LCD drive method is set to the frame reversal method. Line reversal count register: (D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0) On the other hand, when the reset command is used, only the conditions (7) to (15) above are set. As is shown in the "MPU Interface (example for reference)", the RES pin is connected to the Reset pin of the MPU and the initialization of this LSI is made simultaneously with the resetting of the MPU. This LSI always has to be reset using the RES pin at the time the power is switched ON. Also, excessive current can flow through this LSI when the control signal from the MPU is in the Hi-Z state. It is necessary to take measures to ensure that the input terminals of this LSI do not go into the Hi-Z state after the power has been switched ON. When the built-in LCD drive power supply circuit of the ML9050/9051 is not used, it is necessary that RES = "L" when the external LCD drive power supply goes ON. During the period when RES = "L", although the oscillator circuit is operating, the display timing generator would have stopped and the pins CL, FR, FRS, and DOF would have been tied to the "H" level. There is no effect on the pins D0 to D7.
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COMMANDS
MPU Interface
MPU 80-Series 68-Series Read mode Pin RD = "L" Pin R/W = "H" Pin E = "H" Write mode Pin WR = "L" Pin R/W = "L" Pin E = "H"
In the case of the 80-series MPU interface, a command is started by inputting a Low pulse on the RD pin or the WR pin. In the case of the 68-series MPU interface, a command is started by inputting a High pulse on the E pin. Description of commands * Display ON/OFF (Write) This is the command for controlling the turning on or off the LCD panel. The LCD display is turned on when a "1" is written in bit D0 and is turned off when a "0" is written in this bit.
A0 Display ON Display OFF 0 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 1 0
* Display start line set (Write) This command specifies the display starting line address in the display data RAM. Normally, the topmost line in the display is specified using the display start line set command. It is possible to scroll the display screen by dynamically changing the address using the display start line set command.
Line address 0 1 2 . . . 62 63 A0 0 D7 0 D6 1 D5 0 0 0 . . . 1 1 D4 0 0 0 . . . 1 1 D3 0 0 0 . . . 1 1 D2 0 0 0 . . . 1 1 D1 0 0 1 . . . 1 1 D0 0 1 0 . . . 0 1
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* Page address set (Write) This command specifies the page address which corresponds to the lower address when accessing the display data RAM from the MPU side. It is possible to access any required bit in the display data RAM by specifying the page address and the column address.
Page address 0 1 2 . . . 7 8 A0 0 D7 1 D6 0 D5 1 D4 1 D3 0 0 0 . . . 0 1 D2 0 0 0 . . . 1 0 D1 0 0 1 . . . 1 0 D0 0 1 0 . . . 1 0
* Column address set (Write) This command specifies the column address of the display data RAM. The column address is specified by successively writing the upper 4 bits and the lower 4 bits. Since the column address is automatically incremented (by +1) every time the display data RAM is accessed, the MPU can read or write the display data continuously. The incrementing of the column address is stopped at the address 83H.
A0 Upper bits Lower bits Column address 0 1 2 . . . 130 131 a7 0 0 0 . . . 1 1 a6 0 0 0 . . . 0 0 a5 0 0 0 . . . 0 0 a4 0 0 0 . . . 0 0 0 D7 0 D6 0 D5 0 D4 1 0 a3 0 0 0 . . . 0 0 D3 a7 a3 a2 0 0 0 . . . 0 0 D2 a6 a2 a1 0 0 1 . . . 1 1 D1 a5 a1 a0 0 1 0 . . . 0 1 D0 a4 a0
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PEDL9050-02 Semiconductor * Status read (Read)
A0 0 BUSY D7 BUSY D6 D5 D4 D3 0 D2 0 D1 0 D0 0
ML9050/9051
ADC ON/OFF RESET
When BUSY is '1', it indicates that the internal operations are being made or the LSI is being reset. Although no command is accepted until BUSY becomes '0', there is no need to check this bit if the cycle time can be satisfied.
ADC
This bit indicates the relationship between the column address and the segment driver. 0: SEG0 AE SEG131; column address 0H AE 83H 1: SEG131 AE SEG0; column address 0H AE 83H (Opposite to the polarity of the ADC command.)
ON/OFF
This bit indicates the ON/OFF state of the display. (Opposite to the polarity of the display ON/OFF command.) 0: Display ON 1: Display OFF
RESET
This bit indicates that the LSI is being reset due to the RES signal or the reset command. 0: Operating state 1: Being reset
* Display data write (Write) This command writes an 8-bit data at the specified address of the display data RAM. Since the column address is automatically incremented (by +1) after writing the data, the MPU can write successive display data to the display data RAM.
A0 1 D7 D6 D5 D4 D3 D2 D1 D0
Write data
* Display data read (Read) This command read the 8-bit data from the specified address of the display data RAM. Since the column address is automatically incremented (by +1) after reading the data, the MPU can read successive display data from the display data RAM. Further, one dummy read operation is necessary immediately after setting the column data. The display data cannot be read out when the serial interface is being used.
A0 1 D7 D6 D5 D4 D3 D2 D1 D0
Read data
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* ADC Select (segment driver direction select) (Write) Using this command it is possible to reverse the relationship of correspondence between the column address of the display data RAM and the segment driver output. It is possible to reverse the sequence of the segment driver output pin by the command.
A0 Forward Reverse 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 1
* Normal/reverse display mode (Write) It is possible to toggle the display on and off condition without changing the contents of the display data RAM. In this case, the contents of the display data RAM will be retained.
A0 Forward Reverse 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0 1 RAM Data LCD ON Voltage when "H" LCD ON Voltage when "L"
* Display all-on ON/OFF (Write) Using this command, it is possible to forcibly turn ON all the dots in the display irrespective of the contents of the display data RAM. In this case, the contents of the display data RAM will be retained. This command is given priority over the Normal/reverse display mode command.
A0 Normal display state All-on display 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 0 1
The power save mode will be entered into when the Display all-on ON command is executed in the display OFF condition. * LCD Bias set (Write) This command is used for selecting the bias ratio of the voltage necessary for driving the LCD device or panel.
ML9050 1/9 Bias 1/7 Bias ML9051 1/8 Bias 1/6 Bias A0 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 1
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* Read-modify-write (Write) This command is used in combination with the End command. When this command is issued once, the column address is not changed when the Display data read command is issued, but is incremented (by +1) only when the Display data write command is issued. This condition is maintained until the End command is issued. When the End command is issued, the column address is restored to the address that was effective at the time the Read-modify-write command was issued last. Using this function, it is possible to reduce the overhead on the MPU when repeatedly changing the data in special display area such as a blinking cursor.
A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0
* End (Write) This command releases the read-modify-write mode and restores the column address to the value at the beginning of the mode.
A0 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
Restored Column address N N+1 N+2 N+3 .... N+m N End
Read-modify-write mode set
* Reset (Write) This command initializes the display start line number, column address, page address, common output state, voltage V1 adjustment internal resistor ratio, electronic potentiometer function, and the static indicator function, and also releases the read-modify-write mode or the test mode. This command does not affect the contents of the display data RAM. The reset operation is made after issuing the reset command. The initialization after switching on the power is carried out by the reset signal input to the RES pin.
A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0
* Common output state select (Write) This command is used for selecting the scanning direction of the COM output pins.
ML9050 ML9051 A0 0 D7 1 D6 1 D5 0 D4 0 D3 0 1 D2 * * D1 * * D0 * *
Forward COM0 AE COM63 COM0 AE COM47 Reverse COM63 AE COM0 COM47 AE COM0
*: Invalid bits
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PEDL9050-02 Semiconductor * Power control set (Write) This command set the functions of the power supply circuits.
ML9050/9051 Voltage multiplier circuit: OFF Voltage multiplier circuit: ON Voltage adjustment circuit: OFF Voltage adjustment circuit: ON Voltage follower circuits: OFF Voltage follower circuits: ON A0 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 1 0 1 0 1 D1 D0
ML9050/9051
* Voltage V1 adjustment internal resistor ratio set This command sets the ratios of the internal resistors for adjusting the voltage V1.
Resistor ratio Small A0 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 0 . . . Large 0 . . . 1 1 D1 0 0 1 . . . 1 1 D0 0 1 0 . . . 0 1
* Electronic potentiometer (2-Byte command) This command is used for controlling the LCD drive voltage V1 output by the voltage adjustment circuit of the internal LCD power supply and for adjusting the intensity of the LCD display. This is a two-byte command consisting of the Electronic potentiometer mode set command and the Electronic potentiometer register set command, both of which should always be issued successively as a pair. * Electronic potentiometer mode set (Write) When this command is issued, the electronic potentiometer register set command becomes effective. Once the electronic potentiometer mode is set, it is not possible to issue any command other than the Electronic potentiometer register set command. This condition is released after data has been set in the register using the Electronic potentiometer register set command.
A0 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1
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* Electronic potentiometer register set (Write) By setting a 6-bit data in the electronic potentiometer register using this command, it is possible to set the LCD drive voltage V1 to one of the 64 voltage levels. The electronic potentiometer mode is released after some data has been set in the electronic potentiometer register using this command.
V1 Small A0 0 D7 * D6 * D5 0 0 . . . Large 0 . . . 1 1 D4 0 0 0 . . . 1 1 D3 0 0 0 . . . 1 1 D2 0 0 0 . . . 1 1 D1 0 1 1 . . . 1 1 D0 1 0 1 . . . 0 1
*:
Invalid bit
Set the data (*, *, 1, 0, 0, 0, 0, 0) when not using the electronic potentiometer function. Sequence of setting the electronic potentiometer register:
Electronic potentiometer mode set Electronic potentiometer register set The electronic potentiometer mode is released No End of modification? Yes
* Static indicator (2-Byte command) This command is used for controlling the static drive type indicator display. Static indicator display is controlled only by this command and is independent of all other display control commands. One of the electrodes for driving the static indicator LCD is connected to the pin FR and the other pin is connected to the pin FRS. It is recommended to place the wiring pattern for the electrodes for static indicators far from those of the electrodes for dynamic drive. If these interconnection patterns are too close to each other, they may cause deterioration of the LCD device and the electrodes. Since the Static indicator ON command is a two-byte command used in combination with the static indictor register set command, these two commands should always be used together. (The Static indicator OFF command is a single byte command.)
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* Static indicator ON/OFF (Write) When the Static indicator ON command is issued, the Static indicator register set command becomes effective. Once the Static indicator ON command is issued, it is not possible to issue any command other than the Static indicator register set command. This condition is released only after some data is written into the register using the static indicator register set command.
Static indicator OFF ON A0 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 0 1
* Static indicator register set (Write) This command is used to set data in the 2-bit static indicator register thereby setting the blinking state of the static indicator.
Indicator OFF ON (Blinking at about 1sec intervals) ON (Blinking at about 0.5sec intervals) ON (Continuously ON) A0 0 D7 * D6 * D5 * D4 * D3 * D2 * D1 0 0 1 1 D0 0 1 0 1
*: Invalid bits Sequence of setting the static indicator register:
Static indicator ON Static indicator register set The static indicator mode is released No End of modification? Yes
* Line reversal drive (2-byte command) / frame reversal drive selection It is possible to select the LCD driving method between the line reversal drive method and the frame reversal drive methods. When the line reversal method is selected, the command should be used as a two-byte command in combination with the Line reversal number set command and hence these two commands should always be issued successively.
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* LCD Drive method set (Write) This command sets the LCD driving method. Once the line reversal method has been set, no command other than the Line reversal number set command is accepted. This state is released only after some data is set in the register using the Line reversal number set command. The frame reversal set command is a single byte command.
A0 Frame reversal Line reversal 0 D7 1 D6 1 D5 0 D4 1 D3 0 1 D2 * * D1 * * D0 * *
*: Invalid bits * Line reversal number set (Write) When the line reversal method has been set using the LCD drive method set command, it is necessary to set immediately the number of reversed lines.
Number of reversed lines 1 2 . . . 31 32 A0 0 D7 * D6 * D5 * D4 0 0 . . . 1 1 D3 0 0 . . . 1 1 D2 0 0 . . . 1 1 D1 0 0 . . . 1 1 D0 0 1 . . . 0 1
*: Invalid bits * Power save (Compound command) The LSI goes into the power save state when the Display all-on ON command is issued when the LSI is in the display OFF state, and it is possible to greatly reduce the current consumption in this state. The power save state is of two types, namely, the sleep state and the standby state, and the LSI goes into the standby state when the static indicator has been made ON. The display data and the operating mode just before entering the power save mode are retained in both the sleep state and the standby state, and also the MPU can access the display data RAM in these states. The power save mode is released by issuing the Display all-on OFF command.
Static indicator OFF
Static indicator ON
Power save command issue (compound command) Sleep state Power save OFF command (compound command) Display all-on OFF command Static indicator ON command (2-byte command) Sleep state released Standby state released Standby state Power save OFF command (Display all-on OFF command)
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PEDL9050-02 Semiconductor ML9050/9051
* Sleep state In this state, all the operations of the LCD display system are stopped and it is possible to reduce the current consumption to a level near the idle state current consumption unless there are accesses from the MPU. The internal conditions in the sleep state are as follows: (1) The oscillator circuit and the LCD power supply are stopped. (2) All the LCD drive circuits are stopped and the segment and common driver outputs will be at the VSS level. * Standby state All operations of the dynamic LCD display section are stopped, only the static display circuits for the indicators operate and hence the current consumption will be the minimum necessary for static drive. The internal conditions in the standby state are as follows: (1) The power supply circuit for LCD drive is stopped. The oscillator circuit will be operating. (2) The LCD drive circuits for dynamic display are stopped and the segment and common driver outputs will be at the VSS level. The static display section will be operating. When a reset command is issued in the standby state, the LSI goes into the sleep state. * NOP (Write) This is a No Operation command.
A0 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1
* Test (Write) This is a command for testing the IC chip. Do not use this command. When the test command is issued by mistake, this state can be released by issuing a NOP command. This command will be ineffective if the TEST0 pin is open or at the "L" level.
A0 0 D7 1 D6 1 D5 1 D4 1 D3 * D2 * D1 * D0 *
*: Invalid bits
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PEDL9050-02 Semiconductor ML9050/9051
LIST OF COMMANDS
No 1 2 3 4 Operation Display OFF Display ON Display start line set Page address set Column address set (upper bits) Column address set (lower bits) 5 6 7 8 Status read Display data write Display data read ADC Select Forward Reverse 01Address 1011Address 0001Address (upper) 0000Address (lower) Status0000 Write data Read data 10100000 1 0 1 1 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 Dn 76543210 10101110 1 A0 RD WR 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 LCD Display: OFF When D0 = 0 ON When D0 = 1 The display starting line address in the display RAM is set. The page address in the display RAM is set. The upper 4 bits of the column address in the display RAM is set. The lower 4 bits of the column address in the display RAM is set. The status information is read out from the upper 4 bits. Writes data to the display data RAM. Reads data from the display data RAM. Correspondence between the display data RAM address and SEG output. Forward when D0 = 0; reverse when D0 = 1 9 Normal display Reverse display 10 LCD Normal display All-on display 11 LCD Bias set 10100110 1 10100100 1 10100010 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 Normal or reverse LCD display mode. Normal mode when D0 = 0; reverse when D0 = 1 LCD Normal display when D0 = 0; all-on display when D0 = 1 Sets the LCD drive voltage bias ratio. ML9050: 1/9 when D0 = 0 and 1/7 when D0 = 1 ML9051: 1/8 when D0 = 0 and 1/6 when D0 = 1 12 Read-modify-write 13 End 14 Reset 15 Common output state select 11100000 11101110 11100010 11000*** 1*** 16 Power control set 17 Voltage V1 adjustment internal resistor ratio set 00101 Operating state 00100 Resistor ratio setting 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 Incrementing column address During a write: +1; during a read: 0 Releases the read-modify-write state. Internal reset Selects the COM output scanning direction. Forward when D3 = 0; reverse when D3 = 1 Selects the operating state of the internal power supply. Selects the internal resistor ratio. Comment
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PEDL9050-02 Semiconductor ML9050/9051
No
Operation
Dn 76543210 10000001 **Electronic potentiometer value 10101100 1 ******State 11010*** 1*** ***Line number 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 A0 RD WR 0 0 1 1 0 0
Comment Sets the V1 output voltage in the electronic potentiometer register.
18 Electronic potentiometer mode set External potentiometer register set 19 Static indicator ON/OFF Static indicator register set 20 LCD Drive method set Line reversal number set 21 Power save 22 NOP 23 Test
OFF When D0 = 0 ON When D0 = 1 Sets the blinking state. Frame reversal when D3 = 0. Line reversal when D3 = 1. Sets the number of lines ireversed. Compound command of Display OFF and Display all-on.
11100011 1111****
0 0
1 1
0 0
The "No Operation" command. The command for factory testing of the IC chip.
*: Invalid bits
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PEDL9050-02 Semiconductor ML9050/9051
DESCRIPTION OF COMMANDS
Examples of settings for the instructions (reference examples) * Initial setting
VDD-VSS Power supply ON Power supply stabilization RESET Input Wait for more than 20ms *1 Initial settings state (default) *2
Function stabilization using command input (user settings) LCD Bias set ADC Select Common output state selection *3 *4 *5
Line reversal / frame reversal drive method selection *6 Function stabilization using command input (user settings) Setting voltage V1 adjustment internal resistor ratio *7 Electronic potentiometer *8
Function stabilization using command input (user settings) Power control set Initial setting state complete *9
Notes: Sections to be referred to *1: Stabilization time of the internal oscillator *2: Function description "Reset circuit" *3: Command description "LCD Bias set" *4: Command description "ADC Select" *5: Command description "Common output state select" *6: Command description "Line reversal/frame reversal drive select" *7: Function description "Power supply circuit", Command description "Voltage V1 adjustment internal resistor ratio set" *8: Function description "Power supply circuit", Command description "Electronic potentiometer" *9: Function description "Power supply circuit", Command description "Power control set"
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PEDL9050-02 Semiconductor Examples of settings for the instructions (reference examples) * Initial setting Note: After the power is switched ON, this LSI outputs at the LCD drive output pins SEG and COM the VSS potential. If any charge is remaining on the smoothing capacitors connected between the VOUT pin and the pins for the LCD drive voltage outputs (V1 to V5), there may be some abnormality in the display such as temporary blacking out of the display screen when the power is switched ON. The following procedure is recommended for avoiding such abnormalities at the time the power is switched ON. * When using the internal power supply immediately after power-on ML9050/9051
VDD-VSS Power supply ON when the pin RES = "L" Power supply stabilization Release reset state (RES Pin = "H") Initial settings state (default) *1
Function stabilization using command input (user settings) LCD Bias set ADC Select Common output state selection *2 *3 *4 *(a)
Line reversal / frame reversal drive method selection *5 Function stabilization using command input (user settings) Setting voltage V1 adjustment internal resistor ratio *6 Electronic potentiometer *7
Function stabilization using command input (user settings) Power control set Initial setting state complete *8
*(a):
Carry out power control set within 5ms after releasing the reset state. The 5ms duration changes depending on the panel characteristics and the value of the smoothing capacitor. We recommend verification of operation using an actual unit.
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PEDL9050-02 Semiconductor ML9050/9051
Notes: Sections to be referred to *1: Function description "Reset circuit" *2: Command description "LCD Bias set" *3: Command description "ADC Select" *4: Command description "Common output state select" *5: Command description "Line reversal/frame reversal drive select" *6: Function description "Power supply circuit", Command description "Voltage V1 adjustment internal resistor ratio set" *7: Function description "Power supply circuit", Command description "Electronic potentiometer" *8: Function description "Power supply circuit", Command description "Power control set"
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PEDL9050-02 Semiconductor * When not using the internal power supply immediately after power-on
VDD-VSS Power supply ON when the pin RES = "L" Power supply stabilization Release reset state (RES Pin = "H") Initial settings state (default) Start power save mode (compound command) *1 *9 *(a)
ML9050/9051
Function stabilization using command input (user settings) LCD Bias set ADC Select Common output state selection *2 *3 *4
Line reversal / frame reversal drive method selection *5 Function stabilization using command input (user settings) Setting voltage V1 adjustment internal resistor ratio *6 Electronic potentiometer Power save OFF *7 *9 *(b)
Function stabilization using command input (user settings) Power control set Initial setting state complete *8
*(a): Enter the power save state within 5ms after releasing the reset state. *(b): Carry out power control set within 5ms after releasing the power save state. The 5ms duration in *(a) and *(b) changes depending on the panel characteristics and the value of the smoothing capacitor. We recommend verification of operation using an actual unit.
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PEDL9050-02 Semiconductor ML9050/9051
Notes: Sections to be referred to *1: Function description "Reset circuit" *2: Command description "LCD Bias set" *3: Command description "ADC Select" *4: Command description "Common output state select" *5: Command description "Line reversal/frame reversal drive select" *6: Function description "Power supply circuit", Command description "Voltage V1 adjustment internal resistor ratio set" *7: Function description "Power supply circuit", Command description "Electronic potentiometer" *8: Function description "Power supply circuit", Command description "Power control set" *9: The power save state can be either the sleep state or the standby state. Command description "Power save (compound command)"
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PEDL9050-02 Semiconductor * Data display ML9050/9051
End of initial settings Function stabilization using command input (user settings) Display start line set Page address set Column address set *10 *11 *12
Function stabilization using command input (user settings) Display data write *13
Function stabilization using command input (user settings) Display ON/OFF End of data display *14
Notes: Sections to be referred to *10: Command description "Display start line set" *11: Command description "Page address set" *12: Command description "Column address set" *13: Command description "Display data write" *14: Command description "Display ON/OFF" * Power supply OFF (*15)
Any state Function stabilization using command input (user settings) Power save VDD-VSS Power supply OFF *16 *17
Notes: Sections to be referred to *15: The power supply of this LSI is switched OFF after switching OFF the internal power supply. Function description "Power supply circuit" If the power supply of this LSI is switched OFF when the internal power supply is still ON, since the state of supplying power to the built-in LCD drive circuits continues for a short duration, it may affect the display quality of the LCD panel. Always follow the power supply switching OFF sequence. *16: Command description "Power save" *17: Do not enter Reset when switching the power supply OFF.
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PEDL9050-02 Semiconductor * Refresh Use the refresh sequence at regular intervals. ML9050/9051
Refresh sequence Set to the state in which all commands have been set. Test mode release command (F0h) Refresh DDRAM
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PEDL9050-02 Semiconductor ML9050/9051
ABSOLUTE MAXIMUM RATINGS
VSS = 0 V Parameter Power supply voltage Bias voltage Voltage multiplier reference voltage Input voltage Storage temperature range Symbol VDD VBI VIN VI Tstg Condition Ta = 25C Ta = 25C 6-Times multiplication 7-Times multiplication Ta = 25C TCP Chip Rated value -0.3 to +7 -0.3 to +20 -0.3 to +3.3 -0.3 to +2.8 -0.3 to VDD+0.3 -55 to +100 -55 to +125 Unit V V V V C Applicable pins VDD, VSS VOUT, V1 to V5 VIN, VSS All inputs --
Ta:
Ambient temperature
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Bias voltage Voltage multiplier reference voltage Voltage multiplier output voltage Reference voltage Operating temperature range Symbol VDD VBI VIN VOUT VREG0 VREG1 Top -0.05%/C *1 -0.2%/C *1 Condition -- -- 6-Times multiplication 7-Times multiplication Rated value 1.8 to 5.5 6 to 18 1.8 to 3 1.8 to 2.5 18 (3.0) -40 to +85 Unit V V V V V C Applicable pins VDD, VSS VOUT, V1 to V5 VIN, VSS VOUT -- --
*1:
Ta = 25C
VOUT
VIN VCC GND System (MPU) side VDD VSS ML9050/9051
V1 to V4
V5
Note 1: Note 2: Note 3:
The voltages VDD, V1 to V5, and VOUT are values taking VSS = 0 V as the reference. The highest bias potential is V1 and the lowest is VSS. Always maintain the relationship V1 V2 V3 V4 V5 VSS among these voltages.
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PEDL9050-02 Semiconductor ML9050/9051
ELECTRICAL CHARACTERISTICS
DC Characteristics
[Ta = -40 to +85C] Parameter "H" Input voltage "L" Input voltage "H" Output voltage "L" Output voltage "H" Input current "L" Input current LCD Driver ON resistance Current consumption Input pin capacitance
Oscillator frequency
Symbol VIH VIL VOH VOL IIH IIL RON IDDS CIN
Condition
Min 0.8 VDD VSS
Typ
Max VDD 0.2 VDD VDD 0.2 VDD 1.0 3.0 10 5
Unit V V mA kW mA PF kHz kHz kHz kHz
Applicable pins *1 *2 *3 *4 SEG1 to 132 COM1 to 97 VDD
IOH = -0.5mA IOL = 0.5mA VI = VDD VI = 0 V Io = 50 mA Standby Ta = 25C, f = 1MHz Ta = 25C ML9050 Ta = 25C ML9051
0.8 VDD VSS -1.0 -3.0
5 18 18 27 14 22 22 33 17
8 26 26 39 20
Internal oscillation External input Internal oscillation External input
*6 CL*6 *6 CL*6
*1: *2: *3: *4: *5: *6:
A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/ S, DOF, RES, IRS, HPM Pins D0 to D7, FR, FRS, DOF, CL Pins DOF, RES, IRS, HPM Pins A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS, HPM Pins Applicable to the pins D0 to D5, D6 (SCL), D7 (SI), CL, FR, DOF in the high impedance state. COM1 to COM65 in the ML9050, COM1 to COM65 in the ML9051. See Table 24 for the relationship between the oscillator frequency and the frame frequency.
Table 24. Relationship among the oscillator frequency (fOSC), display clock frequency (fLCDCK), and LCD frame frequency (fFR)
Parameter ML9050 ML9051 When the internal oscillator is used When the internal oscillator is not used When the internal oscillator is used When the internal oscillator is not used Display clock frequency (fLCDCK) fOSC/4 External input (fLCDCK) fOSC/8 External input (fLCDCK) LCD frame frequency (fFR) fOSC/4 65 fLCDCK/260 fOSC/8 49 fLCDCK/196
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PEDL9050-02 Semiconductor ML9050/9051
* Operating current consumption value (Ta = 25C) (1) During display operation, internal power supply OFF (The current consumption of the entire IC when an external power supply is used) Display mode: All-white
Model ML9050 ML9051 Symbol IDD Condition VDD = 5 V, V1-VSS = 11 V VDD = 3 V, V1-VSS = 11 V VDD = 3 V, V1-VSS = 11 V VDD = 5 V, V1-VSS = 8 V VDD = 3 V, V1-VSS = 8 V Rated value Min Typ (18) (16) (13) (11) (9) Max Unit mA Remarks
Display mode: Checker pattern
Model ML9050 ML9051 Symbol IDD Condition VDD = 5 V, V1-VSS = 11 V VDD = 3 V, V1-VSS = 11 V VDD = 3 V, V1-VSS = 11 V VDD = 5 V, V1-VSS = 8 V VDD = 3 V, V1-VSS = 8 V Rated value Min Typ TBD TBD TBD TBD TBD Max Unit mA Remarks
(2) During display operation, internal power supply ON Display mode: All-white
Model ML9050 Symbol IDD Condition VDD = 5 V, 3-times voltage multiplication, V1-VSS = 11 V VDD = 3 V, 4-times voltage multiplication, V1-VSS = 11 V ML9051 VDD = 5 V, 3-times voltage multiplication, V1-VSS = 8 V VDD = 3 V, 4-times voltage multiplication, V1-VSS = 8 V VDD = 3 V, 4-times voltage multiplication, V1-VSS = 11 V Normal mode High power mode Normal mode High power mode Normal mode High power mode Normal mode High power mode Normal mode High power mode Rated value Min Typ (67) TBD (81) TBD (35) TBD (43) TBD (72) TBD Max Unit Remarks mA
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PEDL9050-02 Semiconductor Display mode: Checker pattern
Model ML9050 Symbol IDD Condition VDD = 5 V, 6-times voltage multiplication, V1-VSS = 11 V VDD = 3 V, 7-times voltage multiplication, V1-VSS = 11 V ML9051 VDD = 5 V, 6-times voltage multiplication, V1-VSS = 8 V VDD = 3 V, 7-times voltage multiplication, V1-VSS = 8 V VDD = 3 V, 7-times voltage multiplication, V1-VSS = 11 V Normal mode High power mode Normal mode High power mode Normal mode High power mode Normal mode High power mode Normal mode High power mode Rated value Min Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max Unit Remarks mA
ML9050/9051
* Power save mode current consumption, VSS = 0 V, VDD = 3 V10%
Parameter ML9050 Sleep state ML9050 Standby state ML9051 Sleep state ML9051 Standby state Symbol IDDS1 IDDS2 IDDS1 IDDS2 Condition Rated value Min Typ (0.1) (4) (0.1) (4) Max Unit mA Remarks
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PEDL9050-02 Semiconductor Timing Characteristics * System bus read/write characteristics 1 (80-series MPU) ML9050/9051
A0 tAW8 CS1 (CS2= "1") tCYC8 WR, RD tCCLR,tCCLW tCCHR,tCCHW tDS8 D0 to D7 (Write) tACC8 D0 to D7 (Read) tOH8 tDH8 tAH8
[VDD = 4.5 V to 5.5 V, Ta = -40 to +85C] Parameter Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Data hold time RD Access time Output disable time A0 WR RD WR RD D0 to D7 Applicable pins A0 Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100pF Condition Rated value Min 0 0 166 30 70 30 30 30 10 -- 5 Max -- -- -- -- -- -- -- -- -- 70 50 Unit ns
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PEDL9050-02 Semiconductor ML9050/9051
[VDD = 2.7 V to 4.5 V, Ta = -40 to +85C] Parameter Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Data hold time RD Access time Output disable time A0 WR RD WR RD D0 to D7 Applicable pins A0 Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100pF Condition Rated value Min 0 0 300 60 120 60 60 40 15 -- 10 Max -- -- -- -- -- -- -- -- -- 140 100 Unit ns
[VDD = 1.8 V to 2.7 V, Ta = -40 to +85C] Parameter Address hold time Address setup time System cycle time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Data setup time Data hold time RD Access time Output disable time A0 WR RD WR RD D0 to D7 Applicable pins A0 Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100pF Condition Rated value Min 0 0 1000 120 240 120 120 80 30 -- 10 Max -- -- -- -- -- -- -- -- -- 280 200 Unit ns
Note 1:
Note 2: Note 3:
The input signal rise and fall times are specified as 15ns or less. When using the system cycle time for fast speed, the specified values are (tr+tf) (tCYC8-tCCLW-tCCHW) or (tr+tf) (tCYC8-tCCLR-tCCHR). All timings are specified taking the levels of 20% and 80% of VDD as the reference. The values of tCCLW and tCCLR are specified during the overlapping period of CS1 at "L" (CS2 = "H") and the "L" levels of WR and RD, respectively.
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PEDL9050-02 Semiconductor * System bus read/write characteristics 2 (68-series MPU) ML9050/9051
A0 R/W tAW6 CS1 (CS2 = "1") tCYC6 tEWHR,tEWHW E tEWLR,tEWLW tDS6 D0 to D7 (Write) tACC6 D0 to D7 (Read) tOH6 tDH6 tAH6
[VDD = 4.5 V to 5.5 V, Ta = -40 to +85C] Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse width Enable L pulse width Read Write Read Write E E A0 D0 to D7 Applicable pins A0 Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW CL = 100pF Condition Rated value Min 0 0 166 30 10 -- 10 70 30 30 30 Max -- -- -- -- -- 70 50 -- -- -- -- Unit ns
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PEDL9050-02 Semiconductor ML9050/9051
[VDD = 2.7 V to 4.5 V, Ta = -40 to +85C] Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse width Enable L pulse width Read Write Read Write E E A0 D0 to D7 Applicable pins A0 Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW CL = 100pF Condition Rated value Min 0 0 300 40 15 -- 10 120 60 60 60 Max -- -- -- -- -- 140 100 -- -- -- -- Unit ns
[VDD = 1.8 V to 2.7 V, Ta = -40 to +85C] Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable H pulse width Enable L pulse width Read Write Read Write E E A0 D0 to D7 Applicable pins A0 Symbol tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW CL = 100pF Condition Rated value Min 0 0 1000 80 30 -- 10 240 120 120 120 Max -- -- -- -- -- 280 200 -- -- -- -- Unit ns
Note 1:
Note 2: Note 3:
The input signal rise and fall times are specified as 15ns or less. When using the system cycle time for fast speed, the specified values are (tr+tf) (tCYC6-tEWLW-tEWHW) or (tr+tf) (tCYC6-tEWLR-tEWHR). All timings are specified taking the levels of 20% and 80% of VDD as the reference. The values of tEWLW and tEWLR are specified during the overlapping period of CS1 at "L" (CS2 = "H") and the "H" level of E.
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PEDL9050-02 Semiconductor * Serial interface ML9050/9051
tCSS CS1 (CS2 = "1")
tCSH
tSAS
A0
tSAH
tSCYC tSLW
SCL
tSHW
tSDS
SI
tSDH
[VDD = 4.5 V to 5.5 V, Ta = -40 to +85C] Parameter Serial clock period SCL "H" Pulse width SCL "L" Pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL Time CS SI A0 Applicable pins SCL Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rated value Min 200 75 75 50 100 50 50 100 100 Max -- -- -- -- -- -- -- -- -- Unit ns
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PEDL9050-02 Semiconductor ML9050/9051
[VDD = 2.7 V to 4.5 V, Ta = -40 to +85C] Parameter Serial clock period SCL "H" Pulse width SCL "L" Pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL Time CS SI A0 Applicable pins SCL Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rated value Min 250 100 100 150 150 100 100 150 150 Max -- -- -- -- -- -- -- -- -- Unit ns
[VDD = 1.8 V to 2.7 V, Ta = -40 to +85C] Parameter Serial clock period SCL "H" Pulse width SCL "L" Pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL Time CS SI A0 Applicable pins SCL Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rated value Min 400 150 150 250 250 150 150 250 250 Max -- -- -- -- -- -- -- -- -- Unit ns
Note 1: Note 2:
The input signal rise and fall times are specified as 15ns or less. All timings are specified taking the levels of 20% and 80% of VDD as the reference.
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PEDL9050-02 Semiconductor * Display control output timing ML9050/9051
CL(OUT) tDFR
FR
[VDD = 4.5 V to 5.5 V, Ta = -40 to +85C] Parameter FR Delay time Applicable pins FR Symbol tDFR Condition CL = 50pF Rated value Min -- Typ 10 Max 40 Unit ns
[VDD = 2.7 V to 4.5 V, Ta = -40 to +85C] Parameter FR Delay time Applicable pins FR Symbol tDFR Condition CL = 50pF Rated value Min -- Typ 20 Max 80 Unit ns
[VDD = 1.8 V to 2.7 V, Ta = -40 to +85C] Parameter FR Delay time Applicable pins FR Symbol tDFR Condition CL = 50pF Rated value Min -- Typ 50 Max 200 Unit ns
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PEDL9050-02 Semiconductor * Reset input timing ML9050/9051
tRW RES tR
Internal state
Being reset
Reset complete
[VDD = 4.5 V to 5.5 V, Ta = -40 to +85C] Parameter Reset time Reset "L" pulse width Applicable pins -- RES Symbol tR tRW Condition Rated value Min -- 0.5 Typ -- -- Max 0.5 -- Unit ms
[VDD = 2.7 V to 4.5 V, Ta = -40 to +85C] Parameter Reset time Reset "L" pulse width Applicable pins -- RES Symbol tR tRW Condition Rated value Min -- 1 Typ -- -- Max 1 -- Unit ms
[VDD = 1.8 V to 2.7 V, Ta = -40 to +85C] Parameter Reset time Reset "L" pulse width Applicable pins -- RES Symbol tR tRW Condition Rated value Min -- 1.5 Typ -- -- Max 1.5 -- Unit ms
Note 1:
All timings are specified taking the levels of 20% and 80% of VDD as the reference.
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PEDL9050-02 Semiconductor ML9050/9051
MPU INTERFACE
The ML9050/9051 series ICs can be connected directly to the 80-series and 68-series MPUs. Further, by using the serial interface, it is possible to operate the LSI with a minimum number of signal lines. In addition, it is possible to expand the display area by using the ML9050/9051 series LSIs in a multiple chip configuration. In this case, it is possible to select the individual LSI to be accessed using the chip select signals.
* 80-Series MPU VDD VCC A0 A1 to A7 IORQ
MPU
A0 Decoder CS1 CS2 D0 to D7 RD WR RES RESET
VDD
C86
ML9050/9051
D0 to D7 RD WR RES
GND
VSS
P/S VSS
* 68-Series MPU VDD VCC A0 A1 to A15 VMA
MPU
A0 Decoder CS1 CS2 D0 to D7 E R/W RES RESET
VDD
C86
ML9050/9051
D0 to D7 E R/W RES
GND
VSS
P/S VSS
* Serial interface VDD VCC A0 A1 to A7
MPU
A0 Decoder CS1 CS2 SI SCL RES RESET
VDD
C86
ML9050/9051
Can be tied to either level.
Port1 Port2 RES
GND
VSS
P/S VSS
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PEDL9050-02 Semiconductor ML9050/9051
PAD CONFIGURATION
Pad Layout ; ML9050 Chip Size : 11.05 3.39mm
Y 290 291 292 135 134 133
X
334 1 90
91
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pad Name DUMMY DUMMY DUMMY DUMMY FRS FR CL DOF TEST0 GND CS1 CS2 VDD RES A0 GND WR RD VDD DB0 X (mm) -5000 -4888 -4776 -4664 -4552 -4440 -4328 -4216 -4104 -3992 -3880 -3768 -3656 -3544 -3432 -3320 -3208 -3096 -2984 -2872 Y (mm) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD VDD VDD VDD VIN VIN VIN VIN GND GND GND VOUT VOUT X (mm) -2760 -2648 -2536 -2424 -2312 -2200 -2088 -1976 -1896 -1816 -1736 -1656 -1576 -1496 -1416 -1336 -1256 -1176 -1076 -951 Y (mm) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550
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PEDL9050-02 Semiconductor ML9050/9051
Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pad Name VC2+ VC2+ VC4+ VC4+ VC6+ VC6+ VS2- VS2- VS1- VS1- VC5+ VC5+ VC3+ VC3+ VC1+ VC1+ GND GND VRS VRS VDD VDD V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VR VDD VDD TEST1 VDD MS CLS
X (mm) -826 -701 -576 -451 -326 -201 -76 49 174 299 424 549 674 799 924 1049 1174 1299 1424 1549 1674 1799 1924 2049 2174 2299 2424 2549 2674 2799 2924 3049 3174 3299 3424 3549 3674 3786 3898 4010
Y (mm) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550
Pad No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pad Name GND C86 PS VDD HPM GND IRS VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
X (mm) 4122 4234 4346 4458 4570 4682 4794 4906 5018 5130 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340
Y (mm) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1363.2 -1298.2 -1233.2 -1168.2 -1103.2 -1038.2 -973.2 -908.2 -843.2 -778.2 -713.2 -648.2 -583.2 -518.2 -453.2 -388.2 -323.2 -258.2 -193.2 -128.2 -63.2 1.8 66.8 131.8 196.8 261.8 326.8 391.8 456.8 521.8
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PEDL9050-02 Semiconductor ML9050/9051
Pad No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Pad Name COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14
X (mm) 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5037.5 4972.5 4907.5 4842.5 4777.5 4712.5 4647.5 4582.5 4517.5 4452.5 4387.5 4322.5 4257.5 4192.5 4127.5 4062.5 3997.5 3932.5 3867.5 3802.5 3737.5 3672.5 3607.5 3542.5 3477.5 3412.5 3347.5
Y (mm) 586.8 651.8 716.8 781.8 846.8 911.8 976.8 1041.8 1106.8 1171.8 1236.8 1301.8 1366.8 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545
Pad No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54
X (mm) 3282.5 3217.5 3152.5 3087.5 3022.5 2957.5 2892.5 2827.5 2762.5 2697.5 2632.5 2567.5 2502.5 2437.5 2372.5 2307.5 2242.5 2177.5 2112.5 2047.5 1982.5 1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 747.5
Y (mm) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545
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Pad No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Pad Name SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94
X (mm) 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -682.5 -747.5 -812.5 -877.5 -942.5 -1007.5 -1072.5 -1137.5 -1202.5 -1267.5 -1332.5 -1397.5 -1462.5 -1527.5 -1592.5 -1657.5 -1722.5 -1787.5 -1852.5
Y (mm) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545
Pad No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280
Pad Name SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 DUMMY DUMMY DUMMY
X (mm) -1917.5 -1982.5 -2047.5 -2112.5 -2177.5 -2242.5 -2307.5 -2372.5 -2437.5 -2502.5 -2567.5 -2632.5 -2697.5 -2762.5 -2827.5 -2892.5 -2957.5 -3022.5 -3087.5 -3152.5 -3217.5 -3282.5 -3347.5 -3412.5 -3477.5 -3542.5 -3607.5 -3672.5 -3737.5 -3802.5 -3867.5 -3932.5 -3997.5 -4062.5 -4127.5 -4192.5 -4257.5 -4322.5 -4387.5 -4452.5
Y (mm) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545
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PEDL9050-02 Semiconductor ML9050/9051
Pad No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307
Pad Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44
X (mm) -4517.5 -4582.5 -4647.5 -4712.5 -4777.5 -4842.5 -4907.5 -4972.5 -5037.5 -5102.5 -5167.5 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340
Y (mm) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1366.8 1301.8 1236.8 1171.8 1106.8 1041.8 976.8 911.8 846.8 781.8 716.8 651.8 586.8 521.8 456.8 391.8
Pad No. 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334
Pad Name COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS0 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY
X (mm) -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340
Y (mm) 326.8 261.8 196.8 131.8 66.8 1.8 -63.2 -128.2 -193.2 -258.2 -323.2 -388.2 -453.2 -518.2 -583.2 -648.2 -713.2 -778.2 -843.2 -908.2 -973.2 -1038.2 -1103.2 -1168.2 -1233.2 -1298.2 -1363.2
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PAD CONFIGURATION
Pad Layout ; ML9051 Chip Size : 11.05 3.39mm
Y 290 291 292 135 134 133
X
334 1 90
91
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pad Name DUMMY DUMMY DUMMY DUMMY FRS FR CL DOF TEST0 GND CS1 CS2 VDD RES A0 GND WR RD VDD DB0 X (mm) -5000 -4888 -4776 -4664 -4552 -4440 -4328 -4216 -4104 -3992 -3880 -3768 -3656 -3544 -3432 -3320 -3208 -3096 -2984 -2872 Y (mm) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name DB1 DB2 DB3 DB4 DB5 DB6 DB7 VDD VDD VDD VDD VIN VIN VIN VIN GND GND GND VOUT VOUT X (mm) -2760 -2648 -2536 -2424 -2312 -2200 -2088 -1976 -1896 -1816 -1736 -1656 -1576 -1496 -1416 -1336 -1256 -1176 -1076 -951 Y (mm) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550
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Pad No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Pad Name VC2+ VC2+ VC4+ VC4+ VC6+ VC6+ VS2- VS2- VS1- VS1- VC5+ VC5+ VC3+ VC3+ VC1+ VC1+ GND GND VRS VRS VDD VDD V1 V1 V2 V2 V3 V3 V4 V4 V5 V5 VR VR VDD VDD TEST1 VDD MS CLS
X (mm) -826 -701 -576 -451 -326 -201 -76 49 174 299 424 549 674 799 924 1049 1174 1299 1424 1549 1674 1799 1924 2049 2174 2299 2424 2549 2674 2799 2924 3049 3174 3299 3424 3549 3674 3786 3898 4010
Y (mm) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550
Pad No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Pad Name GND C86 PS VDD HPM GND IRS VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
X (mm) 4122 4234 4346 4458 4570 4682 4794 4906 5018 5130 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340
Y (mm) -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1550 -1363.2 -1298.2 -1233.2 -1168.2 -1103.2 -1038.2 -973.2 -908.2 -843.2 -778.2 -713.2 -648.2 -583.2 -518.2 -453.2 -388.2 -323.2 -258.2 -193.2 -128.2 -63.2 1.8 66.8 131.8 196.8 261.8 326.8 391.8 456.8 521.8
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PEDL9050-02 Semiconductor ML9050/9051
Pad No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160
Pad Name COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14
X (mm) 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5340 5037.5 4972.5 4907.5 4842.5 4777.5 4712.5 4647.5 4582.5 4517.5 4452.5 4387.5 4322.5 4257.5 4192.5 4127.5 4062.5 3997.5 3932.5 3867.5 3802.5 3737.5 3672.5 3607.5 3542.5 3477.5 3412.5 3347.5
Y (mm) 586.8 651.8 716.8 781.8 846.8 911.8 976.8 1041.8 1106.8 1171.8 1236.8 1301.8 1366.8 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545
Pad No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54
X (mm) 3282.5 3217.5 3152.5 3087.5 3022.5 2957.5 2892.5 2827.5 2762.5 2697.5 2632.5 2567.5 2502.5 2437.5 2372.5 2307.5 2242.5 2177.5 2112.5 2047.5 1982.5 1917.5 1852.5 1787.5 1722.5 1657.5 1592.5 1527.5 1462.5 1397.5 1332.5 1267.5 1202.5 1137.5 1072.5 1007.5 942.5 877.5 812.5 747.5
Y (mm) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545
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PEDL9050-02 Semiconductor ML9050/9051
Pad No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Pad Name SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94
X (mm) 682.5 617.5 552.5 487.5 422.5 357.5 292.5 227.5 162.5 97.5 32.5 -32.5 -97.5 -162.5 -227.5 -292.5 -357.5 -422.5 -487.5 -552.5 -617.5 -682.5 -747.5 -812.5 -877.5 -942.5 -1007.5 -1072.5 -1137.5 -1202.5 -1267.5 -1332.5 -1397.5 -1462.5 -1527.5 -1592.5 -1657.5 -1722.5 -1787.5 -1852.5
Y (mm) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545
Pad No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280
Pad Name SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 DUMMY DUMMY DUMMY
X (mm) -1917.5 -1982.5 -2047.5 -2112.5 -2177.5 -2242.5 -2307.5 -2372.5 -2437.5 -2502.5 -2567.5 -2632.5 -2697.5 -2762.5 -2827.5 -2892.5 -2957.5 -3022.5 -3087.5 -3152.5 -3217.5 -3282.5 -3347.5 -3412.5 -3477.5 -3542.5 -3607.5 -3672.5 -3737.5 -3802.5 -3867.5 -3932.5 -3997.5 -4062.5 -4127.5 -4192.5 -4257.5 -4322.5 -4387.5 -4452.5
Y (mm) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545
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Pad No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307
Pad Name DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36
X (mm) -4517.5 -4582.5 -4647.5 -4712.5 -4777.5 -4842.5 -4907.5 -4972.5 -5037.5 -5102.5 -5167.5 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340
Y (mm) 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1545 1366.8 1301.8 1236.8 1171.8 1106.8 1041.8 976.8 911.8 846.8 781.8 716.8 651.8 586.8 521.8 456.8 391.8
Pad No. 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334
Pad Name COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COMS0 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY
X (mm) -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340 -5340
Y (mm) 326.8 261.8 196.8 131.8 66.8 1.8 -63.2 -128.2 -193.2 -258.2 -323.2 -388.2 -453.2 -518.2 -583.2 -648.2 -713.2 -778.2 -843.2 -908.2 -973.2 -1038.2 -1103.2 -1168.2 -1233.2 -1298.2 -1363.2
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NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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